1. Field of the Invention
Embodiments of the present invention relate to the field of electronic memory devices. More specifically, embodiments of the present invention relate to improving read after write execution performance for memory systems that employ delayed write data, e.g., a dynamic random access memory (DRAM) device.
2. Related Art
FIG. 1 illustrates a timing diagram 20 of a typical read command (“read”) being executed within a memory device, e.g., a dynamic random access memory (DRAM). In this example: AL=1; tRCD=8; CL=7; RL=(AL+CL)=8; and WL=(RL−1)=7. The read command begins execution by the memory at the read CAS command 22a which is shown at clock cycle 7. At this point, the read address is also presented. However, there is a read latency 24, between the time the CAS command 22a is presented and the time that the data 22b associated with the read command is actually presented by the memory. In the example shown in FIG. 1, the read latency, tRL, is approximately 8 clock cycles because the data 22b is presented at cycle 15. The read data is delayed because the DRAM device needs time to access the data located at the read address and present it onto the bus.
However, for a write command (“write”), no latency is required because the write address and the write data can be presented to the memory device at the same time. Some DRAM manufacturers therefore execute the read with a read data latency but do not impose a write data latency for writes. On the other hand, some DRAM specifications are showing writes with delayed write data by some predetermined number of clocks after the write CAS command. This is done to enable short write after read turnaround times because their CAS commands and data can be pipelined.
FIG. 2A illustrates a timing diagram 26 of a short write after read turnaround time for a DRAM that utilizes delayed write data operation, e.g., the write data is delayed to match the intrinsic read data latency. In this example: Additive Latency (AL)=1; tRCD=8; CAS Latency (CL)=7; Read Latency (RL)=(AL+CL)=8; and Write Latency (WL)=(RL−1)=7. At clock 7 the CAS command 30a for the read is issued. Four clocks later, at clock 11, the CAS command 32a for the write is issued before the read is completed. After the read data latency period 34, at clock 15, the data 30b for the read is presented on the bus. At clock 18, after an imposed write data latency 36, the data 32b corresponding to the write is presented on the bus. By providing the write data latency 36, the DRAM allows the write following the read to be pipelined to increase performance.
Unfortunately, as shown in FIG. 2B, DRAMs that employ a write data delay cause read-after-write times to be on the order of the CAS latency because the DRAM specification requires that the write complete before issuing the subsequent read. In this example: AL=0; tRCD=8; CL=7; RL=(AL+CL)=7; WL=(RL−1)=6; and tCDLR=4. As shown in FIG. 2B, the CAS command 40a for the write is issued at clock 0. The data 40b associated with the write is then presented after the write data latency at clock 6. However, the read CAS command of the subsequent read operation may not be presented before the data 40b for the write is stored in the memory. This is done to prevent stale data from being returned to the subsequent read. Therefore, the subsequent read CAS command 42a is issued at clock 12, and its data 42b is returned at clock 19. Using this DRAM memory, the read is not issued until 12 clocks (2+6+4) after the write command 40a as shown by length 46. A series of NOPs 44 is inserted by the DRAM specification to delay the read instruction. Issuing the read any sooner would possibly return stale data not from the latest write to the read address, or alternatively, could cause address decode contention within the memory device.
However, this delay period 44 inserted for the read-after-write situation of FIG. 2B can severely reduce the performance of the DRAM memory. It would be advantageous to provide the write-after-read pipelining available to the DRAM of FIG. 2A without suffering the performance degradation caused by the read-after-write situation of FIG. 2B.